CMSC 240: Principles of Computer Organization
Instructors:
John Dougherty
Semester & Year: Fall 2016 | Syllabus
Schedule:
- Lecture: MW 11:15 am - 12:45 pm in KINSC E309 XOR TTh 2:30-4:00 in KINSC H108
- Lab Sections: T 9 - 10 am; T 1:30 - 2:30 pm; W 9:30 - 10:30 am; Th 9 - 10 am (enroll in one lab sectionweekly)
Text:
Digital Design and Computer Architecture, second edition (but first is OK),
by David Harris and Sarah Harris
Recommended (or an acceptable alternate text):
Computer Engineering: Hardware Design,
by M. Morris Mano.
"The Haverford Educational RISC Architecture"
by
David Wonnacott
(this booklet is available with a nice cover at the Haverford book store
(the lulu.com version,
but without the shipping cost)
or you can print your own (without the cool cover) from the
HERA web
site).
Requirements:
- Exams (2) covering the three sections of the course:(1) combinational circuits; (2) sequential circuits; and (3) system/microprocessor design.
- Lab exercises, including "live grading" sessions
- Written homework or "mini-homework"
- contributions in class and lab
Department of Computer Science Collaboration Policy
Prerequisites:
CMSC 106 (or 206 at Bryn Mawr).
Math/CS 231 (Discrete Mathematics) is also highly recommended.
Concurrent enrollment in this and two other CMSC lab courses requires
permission of the instructor.
Description: A lecture/laboratory course studying the hierarchical
design of modern digital computers: combinatorial and sequential logic design,
memory and processor organization, instruction sets, assembly language,
elements of operating systems, and advanced topics as time permits (such as
parallel processing)
Lab Assignments and Term Project:
- Lab 0:
Introduction to logisim and Thinking About Circuits
- Lab 1:
Boolean Logic and Combinational Circuits
- Lab 2:
Modular Combinational Circuits
- Lab 3:
Arithmetic and Sequential Circuits
- Lab 4:
High Level Components and Memory
- Lab 5:
Processors, Numbers and Arithmetic
- Lab 6:
HERA assembly into machine code; memory access
- Term Project:
HERA processor, including Branching and Function Calls
